Fujitsu FR60 Hardware Manual page 539

■ If an External Pin Transfer Request is Reentered During Transfer
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For burst, step, and block transfers
While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled.
However, since operation of the external bus control unit and operation of the DMAC are not completely
synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to
enable transfer requests by using DREQ input.
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For a demand transfer
If reloading of the transfer count register is specified when transfer for as many transfers as specified has
been completed, another transfer request is accepted.
■ If Another Transfer Request Occurs During Block Transfer
No request is detected before the transfer of the specified blocks is completed. At the block boundaries,
transfer requests accepted at that time are evaluated and then transfer on the channel with the highest
priority is performed.
■ Transfer Between External I/O and External Memory
As targets of transfer by the DMAC, external I/O and external memory are not distinguished. Specify an
external I/O as a fixed external address. To perform fly-by transfer, set the address of external memory in
the transfer destination address register. For external I/O, use the signal decoded by the DACK output and
RD or WR.
■ AC Characteristics of DMAC
DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the
DMAC. Output timing is synchronized with external bus access. (Refer to the AC standard for the DMAC.)
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