External Level Register (Elvrn) - Fujitsu FR60 Hardware Manual

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External Level Register (ELVRn)

The external level register (ELVRn) specifies how a request is detected.

■ Bit Configuration of External Level Register (ELVRn)

The bit configuration of the external level register is shown below.

ELVR0 address :000042

ELVR1 address :0000D2

2 bits of the ELVRn register are assigned to each of INT0 to INT15, and level settings are as shown below.

Even though the bits of the EIRR are cleared while the request input is level-base operation, the pertinent

bits are set again as long as the input is at the level that is active.

Table 10.2-1 lists the assignment of ELVR.

Table 10.2-1 Assignment of ELVR

A falling edge is always detected at NMI (except in the stop state).

In the stop state, the "L" level is detected.

"L" level indicates the existence of a request.

"H" level indicates the existence of a request.

A rising edge indicates the existence of a request.

A falling edge indicates the existence of a request.

Initial value

Initial value

Initial value

Initial value

Mb91350a series