Structure Of The 16-Bit Reload Timer - Fujitsu FR60 Hardware Manual

7.2.1

Structure of the 16-bit Reload Timer

The clock source can be selected from three internal clocks (machine clocks divided by
2, 8, and 32. However, only ch3 can be selected up to machine clocks divided by 64 and
128.) and external event.
• DMA transfer can be triggered by an interrupt.
• Four channels for the 16-bit reload timer are built-in.
• The MB91F353A/351A/352A/353A do not have timer output (TOT0 to TOT3).
■ 16-bit Reload Timer Registers
The 16-bit reload timer registers are shown below.
15
-
7
Reserved
15
15
14 13 12 11
- CSL2 CSL1
Reserved
(ch3 only)
6 5 4 3
- OUTL RELD INTE
10 9 8
CSL0 Control status register(TMCSR)
Reserved Reserved
2 1 0
UF CNTE TRG
0
16-bit timer register (TMR)
0
16-bit reload register (TMRLR)
287