Fujitsu FR60 Hardware Manual page 460

2
CHAPTER 15 I C INTERFACE
• 7-bit slave address mask register (ISMK)
• Data register (IDAR)
• Clock control register (ICCR)
• Clock disable register (IDBL)
442
15
Address : 00009A ENSB
H
R/W
Initial value→ 0
7
Address : 00009D
7D
H
R/W
Initial value→ 0
15
Address : 00009E
TEST
H
W
Initial value→ 0
7
Address : 00009F
-
H
R
Initial value→ 0
14 13 12 11
SM6 SM5 SM4 SM3
R/W R/W R/W R/W
1 1 1
6 5 4
6D 5D 4D 3D
R/W R/W R/W R/W
0 0 0
14 13 12 11
- EN CS4 CS3
R R/W R/W R/W
0 0 1
6 5 4
- - -
R R R R
0 0 0
10 9 8
SM2 SM1 SM0
R/W R/W R/W
1 1 1 1
3 2 1 0
2D 1D 0
R/W R/W R/W
0 0 0 0
10 9 8
CS2 CS1 CS0
R/W R/W R/W
1 1 1 1
3 2 1 0
- - - DBL
R R R/W
0 0 0 0