Fujitsu FR60 Hardware Manual page 163

[Bit 14] WIE (watch timer interrupt enable)
This bit enables or disables the interrupt request output to the CPU. If this bit and the watch interrupt
request flag bit are "1", a watch timer interrupt request is outputted.
Value
0 Output of watch timer interrupt request disabled (default value)
1 Output of watch timer interrupt request disabled
• This bit is cleared to "0" by a reset (INIT) request.
• Data can be written to and read from this bit.
[Bits 13 to 11] (reserved bits)
These bits are reserved. When writing data to these bits, be sure to write "0". (Writing of "1" to these
bits is prohibited.)
Data read from these bits is undefined.
[Bits 10, 9] WS1, WS0 (watch timer interval select 1, 0)
These bits select the interval of the interval timer.
Select the output bit of the watch timer counter from one of the four types listed in Table 3.12-2 .
Table 3.12-2 Watch Timer Counter Output Bits
WS1 WS0
0 0
0 1
1 0
1 1
• These bits are cleared to "00" by a reset (INIT) request.
• Data can be written to and read from these bits.
[Bit 8] WCL (watch timer clear)
Writing "0" to this bit clears the watch timer to "0".
Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation.
• The value read from this bit is always "1".
Explanation
Interval timer interval (at F
10
2 /F (31.25 ms) (default value)
CL
13
2 /F (0.25s)
CL
14
2 /F (0.50s)
CL
15
2 /F (1.00s)
CL
= 32.768 kHz)
CL
145