Data Register (Idar) - Fujitsu FR60 Hardware Manual

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CHAPTER 15 I C INTERFACE
15.2.8

Data Register (IDAR)

This section describes the data register (IDAR).
■ Data Register (IDAR)
The configuration of the data register (IDAR) is shown below.
[Bits 7 to 0] Data bits (D7 to D0)
Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB.
The writing side of this register has a double buffer. While the bus is busy (BB = 1), write data is loaded
into the register for serial transfer. When the INT bit (IBCR) is cleared or the bus is idle (IBSR BB = 0),
transfer data is loaded into the internal transfer register.
Since data is directly read from the register for serial transfer during reading, receive data in this register
is valid only while the INT bit (IBCR) is set.
462
7
Address : 00009D
7D
H
R/W
Initial value→ 0
6 5 4 3
6D 5D 4D 3D
R/W R/W R/W R/W
0 0 0 0
2 1 0
2D 1D 0
R/W R/W R/W
0 0 0