Fujitsu FR60 Hardware Manual page 432

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
Setting of the communication prescaler (CDCR)
div
3
4
5
6
7
8
These bits are initialized to "000" upon a reset. These bits must not be updated during data transfer.
Five types of internal shift clock and an external shift clock are available. Do not set "110" or "111" in
SMD2, SMD1, and SMD0 as these values are reserved.
If the external shift clock mode is selected, shift operation can be performed for each instruction through
manipulation of the ports that share the SCK5 to SCK7 pins.
[bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable)
The serial I/O interrupt enable bit controls the serial I/O interrupt request as described below.
Value
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request)
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are enabled
(SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the MODE bit. When
"0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to the MODE
bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1" is written to the
STOP bit, the SIR bit is cleared regardless of the MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modify-write
instruction.
414
MD DIV3
1 1
1 1
1 1
1 1
1 1
1 1
0 Serial I/O interrupt disabled [default]
1 Serial I/O interrupt enabled
(Machine clock)
DIV2 DIV1
1 0
1 0
0 1
0 1
0 0
0 0
Meaning
DIV0
1
0
1
0
1
0