Fujitsu FR60 Hardware Manual page 142

CHAPTER 3 CPU AND CONTROL UNITS
■ Watchdog Reset Postpone Register (WPR)
The configuration of the watchdog reset postpone register is shown below:
The watchdog reset postpone register postpones a watchdog reset.
If {A5 } and {5A
H
cleared immediately after {5A
There is no time limit between writing of {A5
after {A5
will not occur.
Table 3.10-1 "Time Intervals for Watchdog Reset Generation" shows the relationship between the time
interval for the watchdog reset generation and RSRR register value.
A watchdog reset is generated if writing for both of these data items is not completed within the indicated
interval. The time until a watchdog reset is generated and the write interval required for suppressing
generation depend on the states of WT1 (bit 9) and WT0 (bit 8) in the RSRR register.
Table 3.10-1 Time Intervals for Watchdog Reset Generation
WT1 WT0
0 0
0 1
1 0
1 1
Note: φ is the frequency of the system base clock. WT1 and WT0 are Bits 9 and 8 of the RSRR and are used to set the
watchdog timer interval.
Clearing occurs automatically while the CPU is not running, such as in the stop, sleep, or DMA transfer
state. If one of these conditions occurs, a watchdog reset is automatically postponed. However, a watchdog
reset is not postponed when an external bus hold request (BRQ) has been accepted. To hold the external
bus for a long time, enter sleep mode and then input a hold request (BRQ).
The value read from this register is undefined.
124
bit
Address: 00000485
H
Initial value (INIT)
Initial value (RST)
} are written successively to this register, the detection FF for the watchdog timer is
H
} is written and the watchdog reset is postponed.
H
} is written, {A5 } must be written again before {5A
H H
Required minimum interval of writing to
the WPR to suppress the generation of a
watchdog reset of the RSRR
φ × 2 16
(initial value)
φ × 2 18
φ × 2 20
φ × 2 22
7 6 5 4
D7 D6 D5 D4
W W W W
X X X X
X X X X
} and {5A }. However, if data other than {5A
H H
Time elapsing between writing of the last
5A
3 2 1
D3 D2 D1
W W W
X X X
X X X
} is written. Otherwise, a clear operation
H
to the WPR and the generation a
H
watchdog reset
φ × 2 16 to φ × 2 17
φ × 2 18 to φ × 2 19
φ × 2 20 to φ × 2 21
φ × 2 22 to φ × 2 23
0
D0
W
X
X
} is written
H