Fujitsu FR60 Hardware Manual page 284

CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
the direction to which counting is changed can be determined.
However, note that when the period of direction change is short and multiple direction changes are
performed in succession, the direction that the flag indicates after the direction change may return to the
original direction so that it appears as if the counting direction has not changed at all in between.
Table 6.1-6 summarizes how the count direction change flag works.
Table 6.1-6 Count Direction Change Flag
CDCF
●
Compare detection flag
The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for a match
during counting up/down, match by occurrence of a reloading event, as well as when the values already
match when counting started.
●
Operations for 8 bits × 2 channels and 16 bits × 1 channel
This module can be used as an 8-bit up/down counter for 2 channels or a 16-bit up/down counter for 1
channel. Setting the M16E bit of the CCRH0 register to 0 sets 8-bit mode for 2 channels. Setting the bit to 1
sets 16-bit mode for one channel.
For operation in 16-bit mode for 1 channel, the registers CSR0, CCRL0, CCRH0 are valid and the CSR1,
CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, ZIN0 pins are enabled as input
pins, while the AIN1, BIN1, and ZIN1 pins are disabled.
266
0 No direction change
1 Counting direction has changed (at least once).
Count direction change detection