Fujitsu FR60 Hardware Manual page 416

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CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE

The bit configuration of the DRCL register is shown below.

Address : ch0 000066

The DRCL register clears a DMAC interrupt source. Write an arbitrary value to the DRCL register to clear

a DMAC interrupt source. Always use byte access to access the DRCL register.

When an interrupt occurs, DMAC transfer terminates and the DMAC retains the DMAC source until the

DMAC interrupt source is cleared.

Even if the various interrupt request flags are cleared by interrupt processing when the DMAC is not

activated, the DMAC interrupt source is retained as it is.

If the DMAC interrupt source remains as it is and DMAC activation is enabled with a UART specified for

the DMAC activation source, the DMAC will be activated and unintended operation executed even if the

interrupt request flags are not set.

Therefore, when the DMAC is activated for the first time and when the UART has already been used using

interrupts that do not activate the DMAC, use this register to clear the DMAC interrupt source. (This

Initial value

Mb91350a series