Fujitsu FR60 Hardware Manual page 470

2
CHAPTER 15 I C INTERFACE
When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR
register to "1") with no start condition detected (BB bit=0) and with the SDA or SCL pin at the "L"
level.
Figure 15.2-1 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL pin
SDA pin
2
I C operation enable state (EN bit=1)
Master mode setting (MSS bit=1)
Arbitration lost detection (AL bit=1)
Bus busy (BB bit)
Interrupt (INT bit)
6. Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
When an instruction which generates a start condition by enabling I
executed (setting the MSS bit in the IBCR register to "1") with the I
master.
This is because, as shown in Figure 15.2-2 , when the other master on the I
communication with I
condition detected (BB bit =0).
452
SCL or SDA pin at "L" level
2
C disabled (EN bit=0), the I
"L"
"L"
1
0
0
2
C operation (EN bit=1) is
2
C bus occupied by another
2
C bus enters the occupied state with no start
2
C bus starts