Fujitsu FR60 Hardware Manual page 605

Table A-1 I/O Map (5 / 10)
Address
+0
000218
H
00021C
H
000220
H
000224
H
000228
H
00022C
H
to
00023C
H
000240
H
000244
H
to
00027C
H
FRLR[R/W]B,H,W
000280
H
------01
000284
H
to
00038C
H
DRLR[R/W]B,H,W
000390
H
------01
000394
H
to
0003EC
H
0003F0
H
0003F4
H
0003F8
H
0003FC
H
DDRG[R/W]B
000400
H
--000000
DDRK[R/W]B
000404
H
00000000
DDRO[R/W]B
000408
H
00000000
00040C
H
*2: Immediately after release of a reset, the available internal RAM area is limited by the functions described in CHAPTER 19 "DATA
INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS". In addition, if the setting for
available area is rewritten, insert at least one NOP instruction immediately after that processing.
*3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed.
*4: The 16 low-order bits (DTC[15:0]) of DMACA0 to 4 can not be byte-accessed.
+1
DMACA3[R/W]B,H,W
000000000000XXXXXXXXXXXXXXXXXXXX
DMACB3[R/W]B,H,W
0000000000000000XXXXXXXXXXXXXXXX
DMACA4[R/W]B,H,W
000000000000XXXXXXXXXXXXXXXXXXXX
DMACB4[R/W]B,H,W
0000000000000000XXXXXXXXXXXXXXXX
0XX00000XXXXXXXXXXXXXXXXXXXXXXXX
________
*2
________
*2
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*3
DDRH[R/W]B
--000000
DDRL[R/W]B
------00
*3
DDRP[R/W]B
---- 0000
Register
+2
*4
*4
________
________
DMACR[R/W]B
________
________
________
________
________
BSD0[W]
BSD1[R/W]
BSDC[W]
BSRR[R]
DDRI[R/W]B
--000000
DDRM[R/W]B
--000000
________
________
APPENDIX A I/O Map
Block
+3
DMAC
Reserved
DMAC
Reserved
Limit on F-Bus
________
RAM capacity
Reserved
Limit on D-Bus
________
RAM capacity
Reserved
Bit search
module
*3
DDRJ[R/W]B
00000000
DDRN[R/W]B
R-bus data
--000000
direction
register
*3
587