Fujitsu FR60 Hardware Manual page 502

CHAPTER 16 DMA CONTROLLER (DMAC)
[Bit 24] DADM (Destination-ADdr. Count-Mode select): Transfer destination address count mode
This bit specifies the address processing for the transfer destination address of the corresponding
channel in each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer destination address count width (DASZ). When the transfer is
completed, the next access address is written to the corresponding address register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is completed.
To make the address always the same, specify "0" or "1" for this bit and set the address count width
(SASZ and DASZ) to "0".
DADM
• When reset: Initialized to "0".
• This bit is readable and writable.
[Bit 23] DTCR (DTC-reg. Reload): Transfer count register reload specification
This bit controls reloading of the transfer count register for the corresponding channel.
If reloading of the counter is enabled by this bit, the count register value is restored to its initial value
after transfer is completed, then DMAC stops and starts waiting for a new transfer request (an activation
request by STRG or IS setting). (If this bit is "1", the DENB bit is not cleared.)
DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation
stops after the transfer is completed even if reload is specified in the address register. The DENB bit is
also cleared in this case.
DTCR
0
1
• When reset: Initialized to "0".
• This bit is readable and writable.
484
0 Increments the transfer destination address. (initial value)
1 Decrements the transfer destination address.
Disables transfer count register reloading (initial value)
Enables transfer count register reloading.
specification
Function
Function