Fujitsu FR60 Hardware Manual page 200

CHAPTER 4 EXTERNAL BUS INTERFACE
[Bits 30, 22, 14] HLD0,1,2 (Hold Wait Setting: HoLD wait control)
These bits control the hold cycle of the read strobe signal on the transfer source access side during
DMA fly-by access.
HLDn
0
1
If "0" is set, the read strobe signal (RD for memory → I/O and IORD for I/O → memory) and the write
strobe signal (IOWR for memory → I/O and WR0 to WR3 and WR for I/O → memory) on the transfer
source access side are outputted at the same timing.
If "1" is set, the read strobe signal is outputted one cycle longer than the write strobe signal to secure a hold
time for data at the transfer source access side when sending it to the transfer destination.
[Bits 29 to 28, 21 to 20, 13 to 12] WR0,1,2 (I/O Idle Cycle setting: I/O Idle Wait)
These bits set the idle cycle for continuous I/O access during DMA fly-by access.
WRn1
0
0
1
1
If one or more cycles is set as the number of idle cycles, cycles equal to the number specified are inserted
after I/O access during DMA fly-by access. During the idle cycles, all CS and strobe output is negated and
the data pin is set to the high impedance state.
[Bits 27 to 24, 19 to 16, 11 to 8]
These bits set the auto-wait cycle for I/O access during DMA fly-by access.
IWn3
0
0
1
Because data is synchronized between the transfer source and transfer destination, the I/O side setting of
the IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger,
is used as the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the
IWnn bits may be inserted.
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Do not insert a hold extension cycle.
Insert a hold extension cycle to extend the read cycle by one cycle.
WRn0
0 0 cycle
1 1 cycle
0 2 cycles
1 3 cycles
IW03 to 00, IW13 to 10, IW23 to 20 (I/O Wait Cycle: I/O access Wait)
IWn2 IWn1
0 0
0 0
...
1 1
Hold wait setting
Setting of the I/O idle cycle
IWn0
0 0 cycle
1 1 cycle
...
1 15 cycles
I/O wait cycle