8/16-Bit Up/Down Counters/Timer Registers - Fujitsu FR60 Hardware Manual

CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
6.1.2

8/16-bit Up/Down Counters/Timer Registers

This section describes the configuration and functions of the registers used by the 8/
16-bit up/down counters/timers.
■ Counter Control Register High/Low ch0 (CCR H/L ch0)
The bit configuration of the counter control register high/low (ch0) (CCRH/L ch0) is shown below.
Address : 0000B4
0000B5
[Bit 15] M16E: 16-bit mode permission setting bit
8 bits × 2 channels/16 bits × 1 channel operation mode selection (switching) bit
M16E
0
1
[Bit 14] CDCF: Count direction change flag
This flag is set when the count direction is changed. When the count direction is changed from up to
down or down to up during counting, this flag is set to "1".
0: Writing "0" clears the setting.
1: Writing "1" is ignored. The value of this bit is not changed.
CDCF
0
1
Note:
The count direction is set to down when the counter is reset. Therefore, CDCF is set to "1" when up
counting is performed immediately after a reset.
If a read modify write instruction is issued, "1" is read from the CDCF bit.
252
bit 15 14 13
M16E CDCF CFIE
H
R/W R/W R/W
H
7 6 5
Reserved CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W R/W R/W
8 bits × 2 channels operation mode (initial value)
16 bits × 1 channel operation mode
Direction has not been changed (initial value).
Direction has been changed once or more.
12 11 10
CLKS CMS1 CMS0 CES1
R/W R/W R/W R/W
4 3 2
R/W R/W R/W R/W
16-bit mode permission setting
Direction change detection
9 8 Initial value
CES0 00000000
B
R/W
1 0 Initial value
00001000
B
R/W