Fujitsu FR60 Hardware Manual page 422

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
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Reception operation in Mode 2
The ORE and RDRF flags are set when the last data (D7) is detected after the reception transfer is
completed, generating an interrupt request to the CPU. The SIDR data is invalid while ORE is active.
Figure 14.1-6 shows the timing of setting ORE and RDRF in Mode 2.
Receive interrupt
404
Figure 14.1-6 Timing of Setting ORE and RDRF (Mode 2)
Data
D5
ORE
RDRF
D6 D7