Fujitsu FR60 Hardware Manual page 190

CHAPTER 4 EXTERNAL BUS INTERFACE
[Bit 7] SREN (ShaRed ENable)
This bit enables or disables sharing of each chip select area by BRQ/BGRNT as indicated in the
following table:
SREN
0
1
In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the bus is open
(during BGRNT=Low output).
In areas where sharing is disabled, chip select output (CSn) is not set to high impedance even though the
bus is open (during BGRNT=Low output).
Access strobe output (AS, RD, WR0, WR1) is set to high impedance only if sharing of all areas enabled by
CSER is enabled.
[Bit 6] PFEN (PreFetch ENable)
This bit enables or disables prefetch of each chip select area as indicated in the following table:
PFEN
0
1
When reading from an area for which prefetching is enabled, the subsequent address is read in advance and
stored in the built-in prefetch buffer. When the stored address is accessed from the internal bus, the look-
ahead data in the prefetch buffer is returned without performing external access.
For more information, see Section "4.7 Prefetch Operation".
[Bit 5] WREN (WRite ENable)
This bit enables or disables writing to each chip select area.
WREN
0
1
If an area for which write operations are disabled is accessed for a write operation from the internal bus, the
access is ignored and no external access at all is performed.
Set the WREN bit of areas for which write operations are required, such as data areas, to "1".
[Bit 4] LEND (Little ENDian select)
This bit sets the byte ordering of each chip select area.
LEND
0
1
Be sure to set the LEND bit of ACR0 to 0. CS0 area supports only the big endian method.
172
Disable sharing by BRQ/BGRNT (CS cannot be high impedance)
Enable sharing by BRQ/BGRNT (CS can be high impedance)
Disable prefetch
Enable prefetch
Disable write
Enable write
Big endian
Little endian
Sharing enable/disable
Prefetch enable/disable
Write enable/disable
Order of bytes