Fujitsu FR60 Hardware Manual page 81

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■ Multiply & Divide Register

The configuration of the multiply & divide register is shown below:

The multiply and divide registers are 32-bit long.

The initial value after reset is undefined.

When multiplication is executed

For a 32-bit-by-32-bit multiplication, the 64-bit long operation result is stored in the multiply and divide

registers as follows:

MDH: High-order 32 bits

MDL: Low-order 32 bits

For a 16-bit-by-16-bit multiplication, the result is stored as follows:

MDH: Undefined

MDL: 32-bit result

When division is executed

At the start of calculation, the dividend is stored in MDL.

If a DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is executed for a division, the result is

stored in MDL and MDH as follows:

MDH: Remainder

MDL: Quotient

Mb91350a series