Bus Status Register (Ibsr) - Fujitsu FR60 Hardware Manual

15.2.1

Bus Status Register (IBSR)

The bus status register (IBSR) is read-only. All bits are cleared when the I
operating (EN = 0 in ICCR).
■ Bus Status Register (IBSR)
The configuration of the bus status register (IBSR) is shown below.
Address : 000095
Initial value→
[Bit 7] BB (Bus Busy)
This bit indicates the status of the I
Value
0
1
[Bit 6] RSC (Repeated Start Condition)
This bit is the repeated START condition detection bit.
Value
0
1
This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition is detected.
[Bit 5] AL (Arbitration Lost)
This bit is the arbitration lost detection bit.
Value
0
1
Write "0" to the INT bit or "1" to the MSS bit of the IBCR register to clear this bit.
[Arbitration loss is detected if]
• The transmission data does not match the data on the SDA line at the rising edge of SCL.
• A repeated START condition is generated in the first bit of the data by another master.
2
• The I
another slave device.
445
7 6
BB RSC
H
R R
0 0
STOP condition detected
START condition detected (bus used)
Repeated START condition not detected
Repeated START condition detected while bus is being used
Arbitration lost not detected
Arbitration lost detected during master transmission
C interface cannot generate a START or STOP condition because the SCL line is driven to L by
5 4 3
AL LRB TRX
R R R
0 0 0
2
C bus.
Function
Function
Function
2
15.2 I C Interface Register
2
C stops
2 1 0
AAS GCA ADT
R R R
0 0 0