Fujitsu FR60 Hardware Manual page 267

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Counter status register (CSR)
The bit configuration of the counter status register (CSR) is shown below.
bit 7
Address : 0000B7 CSTR
H
0000BB
H
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Counter control register (CCRL)
The bit configuration of the counter control register (CCRL) is shown below.
bit 7
Address : 0000B5 Reserved
H
0000B9
H
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Counter control register (CCRH)
The bit configuration of the counter control register (CCRH) is shown below.
bit 15
Address : 0000B4 M16E CDCF
H
bit 15
Address : 0000B8 Reserved
H
6 5 4
CITE UDIE CMPF OVFF UDFF UDF1
6 5 4
CTUT UCRE RLDE UDCC CGSC CGE1
14 13 12 11
CFIE CLKS CMS1 CMS0
14 13 12 11
CDCF CFIE CLKS CMS1 CMS0
3 2 1 0
UDF0 (CSR0, CSR1)
3 2 1 0
CGE0 (CCRL0, CCRL1)
10 9 8
CES1 CES0 (CCRH0)
10 9 8
CES1 CES0 (CCRH1)
Counter status register (channel 0, 1)
Counter control register (channel 0, 1)
Counter control register (channel 0)
Counter control register (channel 1)
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