Timer Control Status Register (Upper) (Tmcsr0/1H) - Fujitsu MB90420/5 (A) Series Hardware Manual

10.4.1 Timer Control Status Register (upper) (TMCSR0/1H)

Upper bits 11 to 8 and lower bit 7 of the timer control status register (TMCSR0/1) select the operation mode
of the 16-bit reload timer and set the operation condition of the 16-bit reload timer. The lower bit 7 (MOD0) is
explained here.
n Timer control status register (upper) (TMCSR0/1H)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
TMCSR0
—
000050
H
TMCSR1
—
000054
H
R/W : Both read and write
— : Unused
X : Undefined
: Initial value
φ
: Machine clock. The values in parentheses are the values when the machine clock is 16 MHz.
Fig. 10.4 Timer Control Status Register (upper) (TMCSR0/1H)
16-BIT RELOAD TIMER
— — —
CSL1 CSL0 MOD2 MOD1 MOD0
— — — R/W R/W R/W R/W R/W
MOD2 MOD1
0 0
0 0
0 1
0 1
1 X
1 X
MOD2 MOD1
X 0
X 0
X 1
X 1
CSL1 CSL0
0 0
0 1
1 0
1 1
Operation Mode Select Bit
(in internal clock mode)
MOD0
Function of Input Pin
0 Trigger disabled
1
0 Trigger input
1
0
Gate input
1
Operation Mode Select Bit
(in event count mode)
MOD0
Function of Input Pin
0 —
1
0 Trigger input
1
Count Clock Select Bit
Function
Internal clock mode
Event count mode
10-9
bit 0 Initial value
(TMCSR: L) ---00000
Effective Edge, Level
—
Rising edge
Falling edge
Both edges
L level
H level
Effective Edge
—
Rising edge
Falling edge
Both edges
Count Clock
/φ (0.125 µs)
1
2
/φ (0.5 µs)
3
2
/φ (2.0 µs)
5
2
External event input
B