Features - Fujitsu FR60 Hardware Manual

CHAPTER 1 OVERVIEW
1.1

Features

This section describes the features of the FR60 family microcontrollers.
■ FR CPU Features
• 32-bit RISC, load/store architecture, five stages pipeline
• Maximum operating frequency of 50 MHz [PLL used: Oscillation at 12.5 MHz]
• 16-bit fixed-length instructions (basic instructions), one instruction per cycle
• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.--instructions
appropriate for embedded applications
• Function entry and exit instructions, multi load/store instructions of register content--instructions
compatible with high-level languages
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instructions compatible with the FR family
■ Bus Interface
• Maximum operating frequency of 25 MHz
• 24-bit address full output (16M bytes space) capability
(21-bit address full output (2M bytes space) capability: MB91F353A/351A/352A/353A)
• 8/16-bit data output
• Prefetch buffer installed
• Use of unused data/address pins as general-purpose I/O ports
• Totally independent 4-area chip select outputs that can be configured in units as small as 64K bytes
• Supported interface for each type of memory
SRAM and ROM/FLASH
Page mode FLASHROM and page mode ROM interface
• Basic bus cycle (2 cycles)
• Automatic wait cycle generator that can be programmed for each area and can insert waits.
• External wait cycle using RDY input
• DMA support of fly-by transfer capable of wait control for independent I/O
(The MB91F353A/351A/352A/353A does not support fly-by transfer.)
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