Fujitsu FR60 Hardware Manual page 143

■ Base Clock Division Setting Register 0 (DIVR0)
The configuration of base clock division setting register 0 is shown below:
Base clock division setting register 0 (DIVR0) controls the divide-by rate of an internal clock in relation to
the base clock.
This register sets the divide-by rates of the CPU, the clocks of an internal bus (CLKB), a peripheral circuit,
and the peripheral bus clock (CLKP).
Note:
An upper-limit frequency for the operation is prescribed for each clock. If the combination of source
clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency
exceeding this upper-limit frequency, operation is unpredictable. Be extremely careful of the order in
which you change the settings when selecting the source clock.
If the setting in this register is changed, the new frequency-divide-by rate takes effect for the clock rate
following the one during which the setting was made.
[Bits 15 to 12] B3, B2, B1, B0 (clkB divide select 3 to 0)
These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clock divide-by
rate of the CPU, internal memory, and internal bus clock (CLKB)
The values written to these bits determine the divide-by rate (clock frequency) for the base clock of the
CPU and internal bus clocks. Select the divide-by rate from the 16 types listed in the table below.
The upper-limit frequency for operation is 50 MHz. Do not set a divide-by rate that results in a
frequency exceeding this limit.
B3 B2 B1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
... ... ...
1 1 1
φ: Frequency of the system base clock
bit 15
Address: 00000486
B3
H
R/W
Initial value (INIT)
Initial value (RST) X
B0 Clock divide-by rate
φ
0
φ × 2 (divided by 2)
1
φ × 3 (divided by 3)
0
φ × 4 (divided by 4)
1
φ × 5 (divided by 5)
0
φ × 6 (divided by 6)
1
φ × 7 (divided by 7)
0
φ × 8 (divided by 8)
1
... ...
φ × 16 (divided by 16)
1
14 13 12
B2 B1 B0
R/W R/W R/W
0 0 0 0
X X X
Clock frequency: if the source oscillation is 12.5
[MHz] and the PLL is multiplied by 4
11 10 9
P3 P2 P1
R/W R/W R/W
0 0 0
X X X
50 [MHz] (initial value)
25 [MHz]
16.7 [MHz]
12.5 [MHz]
10 [MHz]
8.33 [MHz]
7.01 [MHz]
6.25 [MHz]
...
3.13 [MHz]
8
P0
R/W
0
X
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