Icr (Interrupt Control Register) - Fujitsu FR60 Hardware Manual

3.7.2

ICR (Interrupt Control Register)

The interrupt control register (ICR: Interrupt Control Register), located in the interrupt
controller, sets the level of an interrupt request. An ICR is provided for each of the
interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the
CPU through a bus.
■ Configuration of Interrupt Control Register (ICR)
The following shows the configuration of the interrupt control register (ICR) bits.
7
-
[Bit 4] ICR4
ICR4 is always set to "1".
[Bits 3 to 0] ICR3 to 0
These bits are the low-order 4 bits of the interrupt level for the corresponding interrupt source. They can
be read and written to. Together with Bit 4, a value between 16 and 31 can be set in the ICR.
■ Mapping of Interrupt Control Register (ICR)
Table 3.7-2 shows the relationship between interrupt sources, interrupt control register, and interrupt
vectors.
Table 3.7-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors
Interrupt control register
Interrupt
source
Number
IRQ00 ICR00
IRQ01 ICR01
IRQ02 ICR02
... ...
... ...
IRQ45 ICR45
IRQ46 ICR46
IRQ47 ICR47
6 5 4 3
- - ICR4 ICR3
R R/W
Address
00000440
H
00000441
H
00000442
H
...
...
0000046D
H
0000046E
H
0000046F
H
2 1 0
ICR2 ICR1 ICR0
R/W R/W R/W
Corresponding interrupt vector
Number
Hexadecimal Decimal
10
H
11
H
12
H
...
...
3D
H
3E
H
3F
H
[Initial value]
---111111
B
Address
16 TBR + 3BC
17 TBR + 3B8
18 TBR + 3B4
... ...
... ...
61 TBR + 308
62 TBR + 304
63 TBR + 300
H
H
H
H
H
H
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