Table Of Contents - Fujitsu FR60 Hardware Manual

CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features .............................................................................................................................................. 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimensions .......................................................................................................................... 9
1.4 Pin Layout ......................................................................................................................................... 11
1.5 List of Pin Functions ......................................................................................................................... 13
1.6 Input-output Circuit Forms ................................................................................................................ 27
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31
2.1 Precautions on Handling the Device ................................................................................................. 32
2.2 Precautions on Using the Little-Endian Area .................................................................................... 37
2.2.1 C Compiler (fcc911) ..................................................................................................................... 38
2.2.2 Assembler (fasm911) .................................................................................................................. 41
2.2.3 Linker (flnk911) ............................................................................................................................ 42
2.2.4 Debuggers (sim911, eml911, and mon911) ................................................................................ 43
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 45
3.1 Memory Space .................................................................................................................................. 46
3.2 Internal Architecture .......................................................................................................................... 49
3.2.1 Internal Architecture .................................................................................................................... 50
3.2.2 Overview of Instructions .............................................................................................................. 53
3.3 Programming Model ......................................................................................................................... 55
3.3.1 General-Purpose Registers ......................................................................................................... 56
3.3.2 Dedicated Registers .................................................................................................................... 57
3.4 Data Configuration ............................................................................................................................ 64
3.5 Memory Map ..................................................................................................................................... 66
3.6 Branch Instructions ........................................................................................................................... 67
3.6.1 Operations with a Delay Slot ....................................................................................................... 68
3.6.2 Operation without Delay Slot ....................................................................................................... 71
3.7 EIT (Exception, Interrupt, and Trap) ................................................................................................. 72
3.7.1 EIT Interrupt Levels ..................................................................................................................... 73
3.7.2 ICR (Interrupt Control Register) ................................................................................................... 75
3.7.3 SSP (System Stack Pointer) ........................................................................................................ 77
3.7.4 Interrupt Stack ............................................................................................................................. 78
3.7.5 TBR (Table Base Register) ......................................................................................................... 79
3.7.6 EIT Vector Table .......................................................................................................................... 80
3.7.7 Multiple EIT Processing ............................................................................................................... 84
3.7.8 Operations ................................................................................................................................... 86
3.8 Operating Modes .............................................................................................................................. 90
3.8.1 Bus Modes ................................................................................................................................... 91
3.8.2 Mode Settings .............................................................................................................................. 92
3.9 Reset (Device Initialization) .............................................................................................................. 94
3.9.1 Reset Levels ................................................................................................................................ 95
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