Fujitsu FR60 Hardware Manual page 419

■ CLK Synchronous Mode
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Transfer data format
The UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-3 shows the
relationship between send and receive clocks and data.
Writing to SODR
RXE, TXE
When the internal clock (U-TIMER) has been selected, a data receive synchronous clock is automatically
generated as soon as data is received.
While an external clock has been selected, you must check that data exists in the send data buffer SODR
register of the send side UART (TDRE flag is "0") and then supply an accurate clock for one byte. Before
sending starts and after it ends, be sure to set the mark level.
The data length is 8 bits only, and no parity can be added. Only overrun errors are detected because there is
no start or stop bit.
●
Initialization
The following shows the setting values of the control registers required to use CLK synchronous mode.
• SMR register
• MD1, MD0: 10
• CS: Specifies the clock input.
• PFR (port function) register
• SCE: Set to "1" for an internal timer and to "0" for an external clock.
• SOE: Set to "1" for send and to "0" for receive only.
Figure 14.1-3 Transfer Data Format (Mode 2)
SCK
SI, SO
1
LSB
Data that has been transferred is 01001101
0 1 1 0 0 1 0
MSB
Mark
(Mode 2)
.
B
401