Fujitsu FR60 Hardware Manual page 499

[Bits 19 to 16] BLK3 to 0 (BLocK size): Block size specification
These bits specify the block size for block transfer on the corresponding channel. The value specified
by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the
data width setting). If block transfer will not be performed, set 01
ignored during demand transfer. The size becomes "1".)
BLK
XXXX Block size of the corresponding channel
• When reset: Not initialized.
• These bits are readable and writable.
• If "0" is specified for all bits, the block size becomes 16 words.
• During reading, the block size is always read (reload value).
[Bits 15 to 00] DTC (Dma Terminal Count register): Transfer count register
These bits compose a register for storing the transfer count. Each register has 16-bit length.
All registers have a dedicated reload register. When the register is used for a channel that is enabled to
reload the transfer count register, the initial value is automatically written back to the register when the
transfer is completed.
DTC
XXXX Transfer count for the corresponding channel
When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated
transfer count counter and is decremented by "1" (subtraction) after each transfer unit. When DMA transfer
is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus,
the transfer count value during DMA operation cannot be read.
• When reset: Not initialized.
• These bits are readable and writable. Always access DTC using halfword length or word length.
• During reading, the count value is read. The reload value cannot be read.
• When reset: Not initialized.
(size 1). (This register value is
H
Function
Function
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