Fujitsu FR60 Hardware Manual page 281

Figure 6.1-7 Overview of the Operation when the Reload and Compare Functions are Started
0FF
H
Compare match Compare match
RCR
00
H
An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt
outputs can be enabled separately.
The timing for clearing the UDCR is different during counting and when counting is stopped.
Reloading (writing "1" to the CTUT bit) by software is not allowed during counting.
• During counting, if an event for clearing occurs, all the events are synchronized with the count clock.
Figure 6.1-8 shows the timing of UDCR clearing during counting.
UDCR
Clear event
Count clock
Note:
During counting, reloading due to an underflow is performed in synchronization with the count clock.
• When clearing occurs during counting, if counting is stopped in counter clock synchronization wait
state (state of waiting for the count input for synchronization), the clear operations is performed when
counting is stopped.
Figure 6.1-9 shows the timing of UDCR clearing when counting is stopped.
Counter clear Counter clear
Figure 6.1-8 Timing of UDCR Clearing During Counting
0065
H
at the Same Time
Reload Reload
Underflow Underflow
0066 0000
H
Synchronizes with this clock.
Reload Compare match
Underflow Counter clear
0001
H H
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