Fujitsu FR60 Hardware Manual page 439

Figure 14.2-2 Extended I/O Serial Interface Operation Transitions
End of transfer
STRT=0, BUSY=0
MODE=0
STOP=0
&
STRT=1
Tra nsfer
STRT=1, BUSY=1
Figure 14.2-3 shows the schematic diagram for reading from and writing to the serial data register.
Figure 14.2-3 Schematic Diagram for Reading from and Writing to the Serial Data Register
SOT
SIN
Extended I/O
serial interface
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write standby
state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal is generated.
No interrupt signal is generated when SIE is inactive or transfer has been terminated by writing "1" to
STOP.
2. Reading or writing to the serial data register clears the interrupt request and starts serial transfer.
■ Shift Operation Start/Stop Timing and I/O Timing
Start:
Write "0" to the STOP bit and "1" to the STRT bit of SMCS.
Stop:
The system may stop at the end of transfer or when "1" is written to STOP.
- Stop by STOP=1: The system stops with SIR=0 regardless of the MODE bit.
- Stop by end of transfer: The system stops with SIR=1 regardless of the MODE bit.
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and becomes "0" during stop
or R/W standby state. To check the transfer status, read this bit.
Figure 14.2-4 shows the timing of starting and stopping the shift operation based on the internal clock.
STOP=0 & STRT=0
MODE=0
&
STOP=0 STOP=1
&
END
MODE=1 & END & STOP=0
SDR R/W & MODE=1
Data bus
Read
Write
Interrupt output
(2)
STOP=1
STOP=0
&
STRT=1
Serial data register R/W standby
Data bus
Read
Write
(1)
Interrupt input
Data bus
Reset
STOP
STRT=0, BUSY=0
STOP=1
STRT=1, BUSY=0
MODE=1
CPU
Interrupt controller
421