Table D-10 Memory Store
Mnemonic
STRi, @Rj
STRi, @(R13,Rj)
STRi, @(R14,disp10)
STRi, @(R15,udisp6)
STRi, @-R15
STRs, @-R15
STPS, @-R15
STHRi, @Rj
STHRi, @(R13,Rj)
STHRi, @(R14,disp9)
STBRi, @Rj
STBRi, @(R13,Rj)
STBRi, @(R14,disp8)
* : In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
→
disp10/4
o8, disp9/2
→
udisp6/4
o4; udisp6 has no sign.
Table D-11 Register-to-Register Transfer
Mnemonic
MOVRj, Ri
MOVRs, Ri
MOVRi, Rs
MOVPS, Ri
MOVRi, PS
* : Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
Type
OP
CYCLE
A
14
A
10
B
3
C
13
E
17-0
E
17-8
E
17-9
A
15
A
11
B
5
A
16
A
12
B
7
→
→
o8, disp8
o8; disp10, disp9, and disp8 have a sign.
Type
OP
CYCLE
A
8B
1
A
B7
1
A
B3
1
E
17-1
1
E
07-1
c
NZVC
Operation
→
a
----
Ri
(Rj)
→
a
----
Ri
(R13+Rj)
→
a
----
Ri
(R14+disp10)
→
a
----
Ri
(R15+udisp6)
a
----
R15-=4,Ri
a
----
R15-=4, Rs
a
----
R15-=4, PS
→
a
----
Ri
(Rj)
→
a
----
Ri
(R13+Rj)
→
a
----
Ri
(R14+disp9)
→
a
----
Ri
(Rj)
→
a
----
Ri
(R13+Rj)
→
a
----
Ri
(R14+disp8)
NZVC
Operation
→
----
Rj
Ri
→
----
Rs
Ri
→
----
Ri
Rs
→
----
PS
Ri
→
CCCC
Ri
PS
APPENDIX D Instruction Lists
Word
Word
Word
→
(R15)
→
(R15)
Rs: Special register
→
(R15)
Halfword
Halfword
Halfword
Byte
Byte
Byte
Remarks
Transfer between general-purpose
registers
Rs: Special register
Rs: Special register
*
Remarks
*
609