Fujitsu FR60 Hardware Manual page 641

Burst 2-Cycle Transfer
Burst 2-Cycle Transfer ..................................... 497
Burst Fly-by Transfer
Burst Fly-by Transfer ....................................... 498
Burst Length
Burst Length Setting and Prefetch Efficiency
.......................................................... 219
Burst Transfer
Operation Flowchart for Burst Transfer.............. 523
Bus Control Register
Bus Control Register (IBCR) ............................ 448
Bus Converter
32-bit/16-bit Bus Converter................................. 52
Harvard/Princeton Bus Converter ........................ 52
Bus Error
Bus Error ........................................................ 466
Bus Interface
Bus Interface ....................................................... 2
Control Signals on the Ordinary Bus Interface
.......................................................... 189
Bus Mode
Bus Mode.......................................................... 90
Bus Mode 0 (Single-chip Mode).......................... 91
Bus Mode 1 (Internal-ROM/External-bus Mode)
............................................................ 91
Bus Mode 2 (External-ROM/External-bus Mode)
............................................................ 91
Bus Right
Releasing the Bus Right.................................... 228
Bus Status Register
Bus Status Register (IBSR) ............................... 445
Bus Width
Bus Width of Big Endian Data .......................... 192
Bus Width of Little Endian Data........................ 199
Busy
Ready/Busy Signal (RDY/BUSYX)................... 552
BUSYX
Ready/Busy Signal (RDY/BUSYX)................... 552
Byte Access
Byte Access..................................................... 203
Byte Ordering
Byte Ordering .................................................... 64
Overview of Byte Ordering ............................... 188
C
Calculation
Calculation of Baud Rate .................................. 275
CCR
CCR (Condition Code Register) .......................... 58
Counter Control Register High/Low ch0
(CCR H/L ch0) ................................... 252
Counter Control Register High/Low ch1
(CCR H/L ch1) ................................... 256
CDCR
Serial I/O Prescaler Control Register (CDCR)
..........................................................417
Change Point Detection
Change Point Detection.....................................361
Change Point Detection Data Register
Change Point Detection Data Register (BSDC)
..........................................................359
Channel Group
Channel Group .................................................517
Character String Operation
Manipulation of Arrays Other than Character-type
Arrays Using Character String Operation
Functions ..............................................39
Specification of the -K lib Option when Character
String Operation Functions are Used .......40
Characteristic
Characteristics of PPG Timer.............................298
Characteristics of the 8/16-bit Up/Down
Counters/Timers ..................................247
Character-type Array
Manipulation of Arrays Other than Character-type
Array Using Character String Operation
Functions ..............................................39
Chip Erase
Chip Erase .......................................................549
Erasing Data (Chip Erase) From Flash Memory
..........................................................561
Chip Select Enable Register
Configuration of the Chip Select Enable Register
(CSER)...............................................183
Clear Sequence
Operation Initialization Reset (RST) Clear
Sequence ..............................................98
Setting Initialization Reset (INIT) Clear
Sequence ..............................................98
Clearing
Clearing of the Counter for the 16-bit Free-running
Timer .................................................284
Clearing/Updating the Prefetch Buffer ................220
Timing of Clearing of the 16-bit Free-running
Timer .................................................285
Clearing Interrupt
Timing for Clearing Interrupts During DMA .......510
CLK
CLK Synchronous Mode ...................................401
CLK Synchronous Mode
CLK Synchronous Mode ...................................401
CLKB
CPU Clock (CLKB)..........................................108
CLKP
Peripheral Clock (CLKP) ..................................109
CLKR
Clock Source Control Register (CLKR) ..............120
INDEX
623