Dmac Interrupt Control - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.3.16

DMAC Interrupt Control

Independent of peripheral interrupts that become transfer requests, interrupts can also
be outputted for each DMAC channel.
■ Interrupts That Enable DMAC Interrupt Control Outputs
• Transfer end interrupt:
Occurs only when operation ends normally.
• Error interrupt:
Transfer stop request due to a peripheral circuit (error due to a peripheral)
Occurrence of address error (error due to software)
All of these interrupts are outputted according to the meaning of the end code.
An interrupt request can be cleared by writing "000" to DSS2 to "0" (end code) of DMACS. Be sure to
clear the end code by writing "000" before restarting.
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not
cleared and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the order of priority
is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to
the displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
• Reset
• Clearing by writing "000"
• Peripheral stop request or external pin input (DSTP) stop request
• Normal end
• Stopping when address error detected
• Channel selection and control
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