Fujitsu FR60 Hardware Manual page 188

CHAPTER 4 EXTERNAL BUS INTERFACE
(Continued)
ACR6H
0000065A ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx
H
ACR6L
0000065B SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx
H
ACR7H
0000065E ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx
H
ACR7L
0000065F SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx
H
ACR0 to ACR7 (area configuration registers 0 to 7) are used to set the functions of each chip select area.
[Bits 15 to 12] ASZ3:0 (Area Size Bits [3:0])
These bits set the size of each chip select area as indicated in Table 4.2-1 .
Table 4.2-1 Size of Each Chip Select Area as Set with the Area Size Bits
ASZ3 ASZ2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
170
15 14 13 12
7 6 5 4
15 14 13 12
7 6 5 4
ASZ1 ASZ0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
Size of each chip select area
64K bytes (00010000 byte, ASR A[31:16] bits are valid)
H
128K bytes (00020000 byte, ASR A[31:17] bits are valid)
H
256K bytes (00040000 byte, ASR A[31:18] bits are valid)
H
512K bytes (00080000 byte, ASR A[31:19] bits are valid)
H
1M bytes (00100000 byte, ASR A[31:20] bits are valid)
H
2M bytes (00200000 byte, ASR A[31:21] bits are valid)
H
4M bytes (00400000 byte, ASR A[31:22] bits are valid)
H
8M bytes (00800000 byte, ASR A[31:23] bits are valid)
H
16M bytes (01000000 byte, ASR A[31:24] bits are valid)
H
32M bytes (02000000 byte, ASR A[31:25] bits are valid)
H
64M bytes (04000000 byte, ASR A[31:26] bits are valid)
H
128M bytes (08000000 byte, ASR A[31:27] bits are valid)
H
256M bytes (10000000 byte, ASR A[31:28] bits are valid)
H
512M bytes (20000000 byte, ASR A[31:29] bits are valid)
H
1024M bytes (40000000
H
2048M bytes (80000000
H
Initial value
INIT RST Access
xxxxxxxx
B B
xxxxxxxx
B B
xxxxxxxx
B B
xxxxxxxx
B B
byte, ASR A[31:30] bits are valid)
byte, ASR A[31] bit is valid)
R/W
R/W
R/W
R/W