Registers; Control/Status Registers A (Dmaca0-4); Table 2-1: Dmacan - Fujitsu FR Series Application Note

2.3 Registers

2.3.1 Control/Status Registers A (DMACA0-4)

These registers control the operation of the corresponding DMAC channel.
Bit
Name Explanation
No.
31 DMA Enable
DENB
30 PAUS Pause
Software
29 STRG
Trigger
28 IS4
... ... Input Select
IS0
24
23 EIS3
Extended Input
...
...
Select
20 EIS0
19
BLK3
... ... Block Size
16 BLK0
15 DTC15
DMA Terminal
... ...
Count
DTC00
0
1
When the transfer on the corresponding channel reached the specified count, this bit gets cleared to
0.
2
The software transfer request by the STRG bit function is always valid regardless of the setting of
these bits IS and EIS bits.
3
Please refer the hardware manual for the transfer source selection.
4
If all the bits of block size are 0, then the block size is 16 (times one transfer unit).
MCU-AN-300059-E-V11
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
Initial
Value
1
0
0
0
2
0,0,0 01110 -
3
,0,0
0,0,0
3
,0
4
x
x

Table 2-1: DMACAn

- 10 -
Value
Disables DMA operation on the
0
corresponding channel
Enables DMA operation on the
1
corresponding channel
Enables DMA operation on the
0
corresponding channel
Temporarily stops DMA operation
1
on the corresponding channel
0 Disabled
1 DMA transfer request
Selects the source for the transfer
10010 request
0000
Selects the source for the transfer
-
request along with IS4-0 bits
0111
0000
Selects the block size for
-
corresponding DMAC channel
1111
0x0000
Stores the transfer count for
–
corresponding DMAC channel
0xFFFF
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Operation