Fujitsu FR60 Hardware Manual page 492

CHAPTER 16 DMA CONTROLLER (DMAC)
■ Block Diagram
Figure 16.1-2 is a block diagram of the DMA controller (DMAC).
DMA transfer request to
the bus controller
Read
Write
To bus
controller
Access
address
474
Figure 16.1-2 Block Diagram of the DMAC
Counter
Buffer
Selector
DTC 2-stage register DTCR
Counter
Buffer
Selector
Read/write
control
BLK register
DDNO register
DDNO
DSAD 2-stage register
Write back
Write back
DMA activation
source
selection circuit
& request
acceptance
control
Priority circuit
State
transition
circuit
DMA control
SADM,SASZ[7:0]
DDAD 2-stage register
DADM,DASZ[7:0]
Peripheral activation request/stop input
External pin activation request/stop input
DSS[3:0]
To interrupt controller
ERIR,EDIR
Peripheral interrupt clear
TYPE.MOD,WS
SADR
DADR
IRQ[4:0]
MCLREQ