Dmac Ch0 To Ch4 Dmac All-Channel Control Register - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.4

DMAC ch0 to ch4 DMAC All-Channel Control Register

The DMACR register controls the operation of all five DMAC channels. Always use byte
length to access this register.
■ Functions of the DMACR Bits
The functions of the DMACR bits are shown below.
bit 31
DMAE
bit 15
-
[Bit 31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of
the start/stop settings for each channel and the operating status. Any channel carrying out transfer
cancels the requests and stops transfer at a block boundary. All start operations on each channel in a
disabled state are disabled.
If this bit enables DMA operation, start/stop operations are enabled for all channels. Simply enabling
DMA operation with this bit does not activate each channel.
DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force stopping ("0"
write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27-24 of DMACR]. If
forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data
cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of
DMACB].
DMAE
• When reset: Initialized to "0".
• This bit is readable and writable.
490
30 29 28 27
- - PMO1 DMAH [3 : 0]
14 13 11 11
- - - -
0 Disables DMA transfer on all channels. (initial value)
1 Enables DMA transfer on all channels.
26 25 24 23
-
10 9 8 7
- - - -
(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX
Function
22 21 20 19
- - - -
6 5 4 3
- - - -
18 17 16
- - -
2 1 0
- - -
)
B