Fujitsu FR60 Hardware Manual page 194

CHAPTER 4 EXTERNAL BUS INTERFACE
(Continued)
AWR6H
0000066C
W15
H
AWR6L
0000066D
W07
H
AWR7H
0000066E
W15
H
AWR7L
0000066F
W07
H
Registers AWR0 to AWR7 specify various kinds of waits for each chip select area.
The function of each bit depends on the setting of the access type (bits TYP3 to TYP0) for registers ACR0 to ACR7.
■ Normal Access and Address/Data Multiplex Access
A chip select area specified using the following settings for the access type (bits TYP3 to TYP0) of
registers ACR0 to ACR3 operates as an area for normal access or address/data multiplex access.
TYP3
0
0
The following lists the functions of each AWR0 to 3 bit for a normal access or address/data multiplex
access area. Since the initial values of registers other than AWR0 are undefined, set them to their initial
values before enabling each area with the CSER register.
[Bits 15 to 12] W15 to 12 (First Access Wait Cycle)
These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle.
Except for the burst access cycles, only this wait setting is used.
The initial value of the CS0 area is set to 7 (wait). The initial values of the other areas are undefined.
W15
0
0
1
176
31 30 29 28
W14 W13 W12
23 22 21 20
W06 W05 W04
15 14 13 12
W14 W13 W12
7 6 5 4
W06 W05 W04
TYP2 TYP1
0 x
1 x
W14 W13
0 0
0 0
...
1 1
27 26 25 24
W08 xxxxxxxx
W11 W10 W09
19 18 17 16
W00 xxxxxxxx
W03 W02 W01
11 10 9 8
W08 xxxxxxxx
W11 W10 W09
3 2 1 0
W00 xxxxxxxx
W03 W02 W01
TYP0
Normal access (asynchronous SRAM, I/O, and
x
single/page)
Address data multiplex access (8/16-bit bus width
x
only)
W12
0 Auto-wait cycle 0
1 Auto-wait cycle 1
...
1 Auto-wait cycle 15
Initial value
at INIT at RST Access
xxxxxxxx
R/W
B B
xxxxxxxx
R/W
B B
xxxxxxxx
R/W
B B
xxxxxxxx
R/W
B B
Access type
First access wait cycle