Fujitsu FR60 Hardware Manual page 162

CHAPTER 3 CPU AND CONTROL UNITS
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Watch timer
The watch timer is a 15-bit incremental counter that uses the subclock source oscillation as the count clock.
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Counter clear circuit
The counter clear circuit clears the counter not only when the WCL bit of the WPCR register is set to "0"
but also when a reset (INIT) request is generated.
●
Interval timer selector
The interval timer selector selects one of the four frequency-divide outputs of the watch timer counter for
the interval timer. The trailing edge of the selected frequency-divide output becomes an interrupt source.
●
Watch timer control register (WPCR)
The watch timer control register is used to select the interval time, clear the counter, control interrupts, and
check the counter status.
■ Watch Timer Control Register
The configuration of the watch timer register is shown below:
WPCR
bit
0000048C
H
[Bit 15] WIF (watch timer interrupt flag)
This bit is the watch interrupt request flag.
This bit is set to "1" at the trailing edge of the selected frequency-divide output for the interval timer.
If this bit and the watch interrupt request enable bit are "1", a watch timer interrupt request is outputted.
Value
0
1
• This bit is cleared to "0" by a reset (INIT) request.
• Data can be written to and read from this bit. However, only "0" can be written. If an attempt is made to
write "1" to this bit, its value is not changed.
• If a read modify write instruction is issued, "1" is always read from this bit.
144
15 14 13 12
WIF WIE -
R/W R/W
Watch timer interrupt not requested (default value)
Watch timer interrupt requested
11 10 9
- - WS1 WS0
R/W R/W
Explanation
Initial value
8 at INIT at RST
00 xx
WCL
H H
W
Access
R/W