Fujitsu FR60 Hardware Manual page 471

Figure 15.2-2 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software
processing.
1) Execute the instruction that generates a start condition (set the MMS bit to "1").
2) Use, for example, the timer function to wait* for the time for three-bit data transmission at the
2
I C transfer frequency set in the ICCR register.
Example: Time for three-bit data transmission at an I
* : When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1"
without failure after the time for three-bit data transmission at the I
3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0",
respectively, set the EN bit in the ICCR register to "0" to initialize I
bits are not so, perform normal processing.
453
The INT bit interrupt does not occur
Start Condition in the ninth clock cycle.
SLAVE ADDRESS
{1/(100 × 10 3 )} × 3=30µs
ACK DAT
2
C transfer frequency of 100 kHz
2
15.2 I C Interface Register
Stop Condition
ACK
0
0
2
C transfer frequency.
2
C. When the AL and BB