Fujitsu FR60 Hardware Manual page 176

CHAPTER 3 CPU AND CONTROL UNITS
●
Peripheral stop register 2 (RSTOP2)
Peripheral stop register 2 controls the supply of clock signals to the up/down counter, free-running timer,
input capture, and output compare.
The configuration of peripheral stop register 2 is shown below:
RSTOP2
bit
00000496
ST27*
H
Bit Name
15
ST27
14
ST26
13 ST25
12 ST24
11 ST23
10 ST22
9 ST21
8 ST20
*: For the MB91F353A/351A/352A/353A, the settings of the ST27 and ST26 bits are disabled.
158
15 14 13 12
ST26* ST25 ST24
* 0: A clock signal is supplied to output compare channels 6 and 7 (initial value).
1: Supply of the clock signal is stopped.
* 0: A clock signal is supplied to output compare channels 4 and 5 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to output compare channels 2 and 3 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to output compare channels 0 and 1 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to input capture channels 2 and 3 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to input capture channels 0 and 1 (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to the free-running timer (initial value).
1: Supply of the clock signal is stopped.
0: A clock signal is supplied to up/down counter channels 0 and 1 (initial value).
1: Supply of the clock signal is stopped.
11 10 9
ST23 ST22 ST21 ST20
Initial value
8
at INIT at RST Access
00 xx
H H
W