Fujitsu FR60 Hardware Manual page 100

CHAPTER 3 CPU AND CONTROL UNITS
Table 3.7-3 Vector Table (3 / 4)
Interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Timebase timer overflow
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Delayed interrupt source bit
Reserved for system (used in
REALOS)
82
Interrupt number
Decimal
*2
39
*2
40
*2
41
*2
42
*2
43
*2
44
*2
45
*2
46
47
*2
48
*2
49
*2
50
*2
51
*2
52
*2
53
*2
54
*2
55
*2
56
*2
57
*2
58
*2
59
*2
60
*2
61
*2
62
63
64
Interrupt
level
Hexadecimal
27 ICR23
28 ICR24
29 ICR25
2A ICR26
2B ICR27
2C ICR28
2D ICR29
2E ICR30
2F ICR31
30 ICR32
31 ICR33
32 ICR34
33 ICR35
34 ICR36
35 ICR37
36 ICR38
37 ICR39
38 ICR40
39 ICR41
3A ICR42
3B ICR43
3C ICR44
3D ICR45
3E ICR46
3F ICR47
40 -
Default address of
Offset
TBR
360 000FFF60
H H
35C 000FFF5C
H H
358 000FFF58
H H
354 000FFF54
H H
350 000FFF50
H H
34C 000FFF4C
H H
348 000FFF48
H H
344 000FFF44
H H
340 000FFF40
H H
33C 000FFF3C
H H
338 000FFF38
H H
334 000FFF34
H H
330 000FFF30
H H
32C 000FFF2C
H H
328 000FFF28
H H
324 000FFF24
H H
320 000FFF20
H H
31C 000FFF1C
H H
318 000FFF18
H H
314 000FFF14
H H
310 000FFF10
H H
30C 000FFF0C
H H
308 000FFF08
H H
304 000FFF04
H H
300 000FFF00
H H
2FC 000FFEFC
H H