Fujitsu FR60 Hardware Manual page 513

After each transfer (access) operation, the next access address is generated (increment/decrement/fixed
selectable) by the address counter and then restored to the temporary storage buffer. Because the contents
of this temporary storage buffer are written back to the register (DMADA) after each block transfer unit is
completed, the address register (DMADA) value is updated after each block transfer unit is completed,
making it impossible to determine the address in real time during transfer.
■ Transfer Count and Transfer End
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Transfer count
The transfer count register is decremented (-1) after each block transfer unit is completed. When the
transfer count register becomes "0", counting for the specified transfer ends, and the transfer stops with the
end code displayed or is reactivated (1).
Like the address register, the transfer count register is updated only after each block transfer unit.
If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register is
initialized and then waits for transfer (DTCR of DMACB)
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Transfer end
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code
(DSS[2:0] of DMACB).
• End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end
• A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error
• An address error occurred => Error
• A reset occurred => Reset
The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end
source is generated.
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