Setting A Transfer Request - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.3.2

Setting a Transfer Request

The following three types of transfer requests are provided to activate DMA transfer:
• External transfer request pin
• Built-in peripheral request
• Software request
Software requests can always be used regardless of the settings for other requests.
■ External Transfer Request Pin
A transfer request is generated by input to the input pin prepared for a channel.
The MB91350A supports channels 0 to 2 (DREQ0, 1, and 2).
If the input is valid at this point, the following sources are selected depending on the settings for the
transfer type and the start source:
[Edge detection]
If the transfer type is block, step, or burst transfer, select edge detection:
• Falling edge detection:
• Rising edge detection:
If the transfer type is demand transfer, select level detection:
• "H" level detection:Set with the transfer source selection register. Set when the IS4 to IS0 bits of
• "L" level detection: Set with the transfer source selection register. Set when the IS4 to IS0 bits of
Note: The MB91F353A/351A/352A/353A cannot use the external transfer request pin.
■ Built-in Peripheral Request
A transfer request is generated by an interrupt from the built-in peripheral circuit.
For each channel, set the peripheral's interrupt by which a transfer request is generated (when the IS4 to
IS0 bits of DMACA are 1xxxx).
The built-in peripheral request cannot be used together with an external transfer request.
Note:
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU,
disable interrupts from the interrupt controller (ICR register).
■ Software Request
A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).
The software request is independent of the above two types of transfer request and can always be used.
If a software request occurs concurrently with activation (transfer enable request), a DMA transfer request
is outputted to the bus controller immediately and transfer is started.
496
Set with the transfer source selection register. Set when the IS4 to IS0 bits of
DMACA are 01110.
Set with the transfer source selection register. Set when the IS4 to IS0 bits of
DMACA are 01111.
DMACA are 01110.
DMACA are 01111.