Fujitsu FR60 Hardware Manual page 106

CHAPTER 3 CPU AND CONTROL UNITS
■ Operation of Step Trace Trap
Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every
time an instruction is executed.
[Step trace trap detection conditions]
1. T flag =1
2. There is no delayed branch instruction.
3. A processing routine other than the INTE instruction or a step trace trap is in progress.
4. If the above conditions are met, a break occurs between instruction operations.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of next instruction → (SSP)
5. "00100" → ILM
6. "0" → S flag
7. (TBR+3CC
Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIT occurs due to
the INTE instruction.
In FR family microcontrollers, a trap occurs for the instruction that follows the instruction that set the T
flag.
■ Operation of Undefined Instruction Exception
If, during instruction decode, an undefined instruction is detected, an undefined instruction exception
occurs.
[Undefined instruction exception detection conditions]
1. An undefined instruction is detected during instruction decode.
2. The instruction is not located in the delay slot (it does not immediately follow the delayed branch
instruction).
3. If the above conditions are met, an undefined instruction exception and a break occur.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC → (SSP)
5. "0" → S flag
6. (TBR+3C4
The PC value to be saved is the address of an instruction that detected an undefined instruction exception.
88
) → PC
H
) → PC
H