Overview - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.1

Overview

This module implements DMA (Direct Memory Access) transfer on FR family devices.
When this module is used to control DMA transfer, various data transfer operations can
be executed at high speed by bypassing the CPU, enhancing system performance.
■ Hardware Configuration of the DMAC
This module mainly consists of the following blocks:
• Five independent DMA channels
• 5 channel independent access control circuit
• 32-bit address registers (reload specifiable, two registers for each channel)
• 16-bit transfer count register (reload specifiable, one register for each channel)
• 4-bit block count register (one for each channel)
• External transfer request input pins: DREQ0, DREQ1, and DREQ2 (for ch0, 1, and 2 only)
Note: The MB91F353A/351A/352A/353A do not have an external interface.
• External transfer request acceptance output pins: DACK0, DACK1, and DACK2 (for ch0, 1, and 2
only)
Note: The MB91F353A/351A/352A/353A do not have an external interface.
• DMA end output pins: DEOP0, DEOP1, and DEOP2 (for ch0, ch1, and ch2 only)
Note: The MB91F353A/351A/352A/353A do not have an external interface.
• Fly-by transfer (memory to I/O and I/O to memory) (for ch0, ch1, and ch2 only)
Note: The MB91F353A/351A/352A/353A do not support fly-by transfer.
• 2-cycle transfer
■ Main DMAC Functions
Data transfer using this module mainly consists of the following functions:
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Data can be transferred independently over multiple channels (5 channels)
• Priority (ch0>ch1>ch2>ch3>ch4)
• The priority can be rotated between ch0 and ch1.
• DMAC start sources
External dedicated pin input (edge detection/level detection for ch0, 1, and 2 only)
Note: The MB91F353A/351A/352A/353A do not have an external interface.
Built-in peripheral requests (shared interrupt requests, including external interrupts)
Software request (register write)
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