Fujitsu FR60 Hardware Manual page 538

CHAPTER 16 DMA CONTROLLER (DMAC)
■ Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel
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For burst, step, block, and demand transfers
Operation in which transfer is continued over the same channel by the DREQ pin input cannot be
guaranteed. If DREQ is reasserted at the fastest timing to clear requests retained internally after the transfer
ends, at least one system clock cycle (one CLK output cycle) is provided to detect transfer requests for
other channels. If, as a result, a transfer request for another channel with a higher priority is detected,
transfer on that channel will be started.
Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer
requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when
the DACK pin output is asserted.
■ Timing of DACK Pin Output
The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is
being performed.
The output of DACK is basically synchronized with the address output of external bus access timing. To
use DACK output, it is necessary to enable the DACK output with a port.
■ Timing of the DEOP Pin Output
The DEOP output of this DMA indicates that DMA transfer for the specified number of times of the
accepted channel has been completed.
DEOP output is outputted when access to an external area of the last transfer block starts. Thus, if any
value other than "1" is set (block transfer mode) as the block size, DEOP is outputted when the last data of
the last block is transferred. In this case, the acceptance of the next DREQ is already started even during
transfer (before DEOP output) if the DACK pin output is asserted.
The DEOP output is synchronized with external bus access timing controlled with RD or WR. However, if
the transfer source/transfer destination is internal access, DEOP is not outputted. The DEOP output is used,
it is necessary to enable the DEOP output using the port resister.
■ Timing of the DSTP Pin Input
Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimum effective
pulse width of five system clock cycles (=1/2θ, two cycles of the CPU system clock).
As with DREQ, we recommend that you use DSTP input timing in synchronization with external access
(Use the DACK output and the signal decoded by RD or WR).
Use the pin input to force DMA transfer to stop. Although transfer can be forced to stop by using this pin
input, the status register (DSS[2:0] of DMACB) indicates "Transfer stop request" and is handled as an
error. If interrupts are enabled, interrupts will occur.
Since this function is shared with the DEOP pin, both functions cannot be used. Set switching of functions
with the port register.
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