Nand Flash/Pc Card Control Registers - ST STM32F40 Series Reference Manual

RM0090
32.6.8

NAND Flash/PC Card control registers

The NAND Flash/PC Card control registers have to be accessed by words (32 bits).
PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)
Address offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4
Reset value: 0x0000 0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:20
Bits 19:17 ECCPS: ECC page size.
Bits 16:13 TAR: ALE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR: CLE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7
Bits 6 ECCEN: ECC computation logic enable bit
Bits 5:4 PWID: Databus width.
ECCPS
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Reserved, must be kept at reset value.
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Reserved, must be kept at reset value.
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Defines the external memory device width.
00: 8 bits (default after reset)
01: 16 bits (mandatory for PC Card)
10: reserved, do not use
11: reserved, do not use
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
9
TAR TCLR
8 7 6 5 4 3 2
PWID
Res.
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