Figure 407. Modea Read Accesses; Figure 408. Modea Write Accesses - ST STM32F40 Series Reference Manual

RM0090
Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 407. ModeA read accesses

1. NBL[1:0] are driven low during read access.

Figure 408. ModeA write accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
Memory transaction
ADDSET DATAST
HCLK cycles HCLK cycles
Memory transaction
ADDSET
HCLK cycles
data driven
by memory
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
ai15559
ai15560
1330/1422