Table 210. Fsmc_Btrx Bit Fields - ST STM32F40 Series Reference Manual

RM0090
Table 209. FSMC_BCRx bit fields (continued)
Bit No.
1
0

Table 210. FSMC_BTRx bit fields

Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that
WAIT can be detected 4 HCLK cycles before the end of memory transaction. The following
cases must be considered:
Bit name
MUXEN 0x1
MBKEN 0x1
Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles for
DATAST
read accesses and DATAST+1 HCLK cycles for write accesses).
ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 1.
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
Value to set
Value to set
1342/1422