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RM0090
Table 194. NOR Flash/PSRAM controller: example of supported memories
Device
PSRAM
(multiplexed
I/Os and
nonmultiplexed
I/Os)
SRAM and
ROM
32.5.3
General timing rules
Signals synchronization
●
All controller output signals change on the rising edge of the internal clock (HCLK)
●
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
and transactions (continued)
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
Doc ID 018909 Rev 4
Flexible static memory controller (FSMC)
AHB
Memory
R/W
data
data size
size
R
8
16
W
8
16
R
16
16
W
16
16
R
32
16
W
32
16
R
-
16
R
8
16
R
16
16
R
32
16
W
8
16
W
16/32
16
R
8 / 16
16
W
8 / 16
16
R
32
16
W
32
16
Allowed/
not
Comments
allowed
Y
Y
Use of byte lanes NBL[1:0]
Y
Y
Split into 2 FSMC
Y
accesses
Split into 2 FSMC
Y
accesses
N
Mode is not supported
N
Y
Y
Y
Use of byte lanes NBL[1:0]
Y
Y
Y
Use of byte lanes NBL[1:0]
Split into 2 FSMC
Y
accesses
Split into 2 FSMC
accesses.
Y
Use of byte lanes NBL[1:0]
1326/1422
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